Some metal-insulator-semiconductor (MIS) devices include a gate located in a trench that extends downward from the surface of a semiconductor substrate (e.g., silicon). The current flow in such devices is primarily vertical and, as a result, the cells can be more densely packed. All else being equal, this increases the current carrying capability and reduces the on-resistance of the device. Devices included in the general category of MIS devices include metal-oxide-semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and MOS-gated thyristors.
Trench MOSFETs, for example, can be fabricated with a high transconductance (gm,max) and low specific on resistance (Ron), which are important for optimal linear signal amplification and switching. One of the most important issues for high frequency operation, however, is reduction of the MOSFET's internal capacitances. The internal capacitances include the gate-to-drain capacitance (Cgd), which is also called the feedback capacitance (Crss), the input capacitance (Ciss), and the output capacitance (Coss).
FIG. 1 is a cross-sectional view of a conventional n-type trench MOSFET 10.
In MOSFET 10, an n-type epitaxial (“N-epi”) layer 14 is grown on an N+ substrate 12. N-epi layer 14 may be a lightly doped layer, that is, an N31  layer. A p-type body region 16 separates N-epi layer 14 from N+source regions 18. Current flows vertically through a channel (denoted by the dashed lines) along the sidewall of a trench 20. The sidewall and bottom of trench 20 are lined with a thin gate insulator 22 (e.g., silicon dioxide). Trench 20 is filled with a conductive material, such as doped polysilicon, which forms a gate 24. Trench 20, including gate 24 therein, is covered with an insulating layer 26, which may be borophosphosilicate glass (BPSG). Electrical contact to source regions 18 and body region 16 is made with a conductor 28, which is typically a metal or metal alloy. A body contact region 30 facilitates ohmic contact between metal 28 and P body 16. Gate 24 is contacted in the third dimension, outside of the plane of FIG. 1.
A significant disadvantage of MOSFET 10 is a large overlap region formed between gate 24 and N-epi layer 14, which subjects a portion of thin gate insulator 22 to the drain operating voltage. The large overlap limits the drain voltage rating of MOSFET 10, presents long term reliability issues for thin gate insulator 22, and greatly increases the gate-to-drain capacitance, Cgd, of MOSFET 10. In a trench structure, Cgd is larger than in conventional lateral devices, limiting the switching speed of MOSFET 10 and thus its use in high frequency applications.
One possible method to address this disadvantage is described in application Ser. No. 09/591,179 and is illustrated in FIG. 2. FIG. 2 is a cross-sectional view of a trench MOSFET 40 with an undoped polysilicon plug 42 near the bottom of trench 20. MOSFET 40 is similar to MOSFET 10 of FIG. 1, except for polysilicon plug 42, which is isolated from the bottom of trench 20 by oxide layer 22 and from gate 24 by oxide layer 44. The sandwich of oxide layer 22, polysilicon plug 42, and oxide layer 44 serves to increase the distance between gate 24 and N-epi layer 14, thereby decreasing Cgd.
In some situations, however, it may be preferable to have a material that is a better insulator than undoped polysilicon in the bottom of trench 19 to minimize Cgd for high frequency applications.
One possible method to address this issue is described in application Ser. No. 09/927,320 and is illustrated in FIG. 3. FIG. 3 is a cross-sectional view of a trench MOSFET 50 with a thick oxide layer 52 near the bottom of trench 20. Thick oxide layer 52 separates gate 24 from N-epi layer 14. This circumvents the problems that occur when only thin gate insulator 15 separates gate 24 from N-epi layer 14 (the drain) as in FIG. 1. Thick oxide layer 52 is a more effective insulator than polysilicon plug 42 as shown in FIG. 2, and this decreases the gate-to-drain capacitance, Cgd, of MOSFET 50 compared to MOSFET 40 of FIG. 2.
Nonetheless, the solution of FIG. 3 still has a thin gate oxide region 54 between body region 16 and thick oxide layer 52. This is because the lower junction of body region 16 and the top edge of thick oxide layer 52 are not self-aligned. If body region 16 extends downward past the top edge of thick oxide layer 52, MOSFET 50 could have a high on-resistance, Ron, and a high threshold voltage. Since this alignment is difficult to control in manufacturing, a substantial margin of error must be allowed to prevent an overlap between body region 16 and thick oxide layer 52, and this can lead to significant gate-to-drain overlap in thin gate oxide region 54. Thin gate region 54 also exists in MOSFET 40 of FIG. 2, between body region 16 and polysilicon plug 42. Thus, Cgd can still be a problem for high frequency applications. Accordingly, a trench MOSFET with decreased gate-to-drain capacitance, Cgd, and better high frequency performance is needed.
Another problem with trench MIS devices relates to the strength of the electric field at the comer of the trench, represented, for example, by comer 56 shown in FIG. 1. The field strength is at a maximum at the comer of the trench, and therefore this is normally the location at which avalanche breakdown occurs. Avalanche breakdown generally leads to the generation of hot carriers, and when breakdown occurs near the gate oxide layer, the hot carriers may be injected into the gate oxide layer. This can damage or rupture the gate oxide layer and presents long-term reliability problems for the device. It is preferable for breakdown to take place in the bulk silicon, away from the gate oxide layer.
One technique for reducing the strength of the electric field at the comers of the trench and promoting breakdown in the bulk silicon away from the trench is taught in U.S. Pat. No. 5,072,266. This technique is illustrated in FIG. 4, which shows a MOSFET 60 MOSFET 60 is similar in MOSFET 10 of FIG. 1 except that a deep P+ diffusion 62 extends downward from the P body 16 to a level below the bottom of trench 20. Deep P+ diffusion 62 has the effect of shaping the electric field in such a way as to reduce its strength at the comer 56 of the trench.
While the technique of U.S. Pat. No. 5,072,266 improves the breakdown performance of the MOSFET, it sets a lower limit on the cell pitch, shown as “d” in FIG. 4, because if the cell pitch is reduced too much, dopant from the deep P+ diffusion will get into the channel region of the MOSFET and increase its threshold voltage. Reducing the cell pitch increases the total perimeter of the cells of the MOSFET, providing a greater gate width for the current, and thereby reduces the on-resistance of the MOSFET. Thus, the net effect of using the technique of the Bulucea patent to improve the breakdown characteristics of the MOSFET is that it becomes more difficult to reduce the on-resistance of the MOSFET.
To summarize, there is a clear need for an MIS structure that provides a low on-resistance and threshold voltage and yet is capable of high-frequency operation.